1. Field of the Invention
The invention relates in general to a method for preventing a semiconductor device from being damaged, and more particularly to a method for avoiding plasma damage of a semiconductor device.
2. Description of the Related Art
Most of device damages or wafer defects in fabrication usually result from plasma process. Unfortunately, plasma processes are very essential in semiconductor fabrication, such dry etching or doping processes. During the plasma processes, the wafer is bombard by energetic ions and results in a damage. In addition, since the plasma ions carry a lot of charges, the wafer may also be damaged due to static charge accumulation. For example, energetic plasma ions can penetrate through a gate to damage the gate, and further leave their charges inside the gate. These charges from the ions accumulate in a gate oxide layer, resulting in a degradation of its isolation performance. A device current leakage is therefore induced. All these various kinds of damage resulting from plasma processes are called plasma process induced damage (PPID).
For example, before forming metal layers, a transistor having a gate structure is formed on a semiconductor substrate. Plasma can penetrate the gate structure and then damage a gate oxide layer under the gate structure. Furthermore, charge ions from the plasma are easily trapped in the gate oxide layer. When the charge ions accumulate to a certain level, the charge ions then penetrate through the gate oxide layer to the substrate. This degrades the isolation of the gate oxide layer and induces leakage of the semiconductor device, especially of a semiconductor device having a N-well.
Additionally, in an integrated circuit, after the formation of certain devices, there are still some processes to be performed to complete the circuit layout. For example, after a PMOS or an NMOS is formed on a substrate, to obtain an electrical connection between PMOS or NMOS and other devices or terminals, a conductive layer is formed and patterned. When patterning the conductive layer, an etching step is inevitable. The plasma or other charged particles used to etch the conductive layer very often damage the NMOS or PMOS formed on the substrate.
For example, a P-type substrate comprises an N-well therein. The P-type substrate is typically placed on or connected to a chuck which is grounded. Therefore, any charged carriers coming from the plasma can be directed to the chuck to be grounded via the P-type substrate. However, if the charged carriers are absorbed by the N-well, these carriers have no path for dissipation or neutralization. As a result, the charged carriers accumulate in the N-well, and thus the electrical characteristics of the N-well or even the quality of gate oxide formed thereon is seriously degraded.
In addition since the N-well is formed in and adjacent to the P-type substrate a depletion region is formed between the P-type substrate and the N-well. A potential difference is caused between the P-type substrate and the N-well. Therefore, if a protection structure across the N-well and the P-type substrate is formed to resolve the problems caused by plasma damage, with this potential difference, the performance and electrical characteristics will be degraded.